| Peter G. Sassone | |
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13408 Creole Cove |
peter at wreck.org 512.922.1211 |
| Microarchitect
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Qualcomm Corporation, Austin TX |
Oct. 2010-present |
| Microarchitect for Qualcomm Hexagon digital signal processor. Responsible for creating and implementing a methodology for validating the performance of the core, identifying microarchitectural enhancements, and improving the software model's correlation. | ||
| Performance Architect
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Intel Corporation, Austin TX |
May. 2009-Sep. 2010 |
| Senior performance architect for Atom processor team. Authored static translation and profiling tool from competitor ISA to Intel architecture, and assisted in competitive analysis versus that competitor. Modeled several microarchitectural features and authored a proposed ISA extension for future Atom cores. | ||
| Performance Architect
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Intel Corporation, Austin TX |
Dec. 2006-May 2009 |
| Co-team leader of performance modeling team for Xeon HPC part. Owned modeling of the front-end, integer-execution, and vector-execution. Implemented and validated a 500+ vector instruction set in the functional simulator, helped author an assembler extension for these instructions, and brought up infrastructure for compiling and testing workloads with the new ISA. | ||
| Research
Scientist
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Intel Corporation, Austin TX |
July. 2005-Dec. 2006 |
| Researcher for Intel's Microprocessor Research Labs, studying micro-architectural techniques for more aggressive scheduling in out-of-order pipelines. Work culminated in ISCA-34 paper on larger and faster matrix schedulers. | ||
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Research Assistant
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Georgia Inst of Technology, Atlanta GA |
Jan. 2001-Aug 2005 |
| Research Assistant for Electrical and Computer Engineering, under the supervision of Dr. D. Scott Wills. Research topics include the applicability of off-the-shelf hardware for massive parallel and distributed processing and the characterization of modern board-level communication protocols. | ||
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Head Teaching Assistant
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Georgia Inst of Technology, Atlanta GA |
Jan. 1998-May 2000 |
| Head Teaching Assistant for Computer Science 1322, Introduction to Programming in Java. Supervisor responsibilities included supervising 50+ teaching assistants, hiring new ones, and writing course assignments such as projects, tests, and finals. | ||
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Computer Architecture |
A Segmented Bloom Filter Algorithm for Efficient Predictors M. Breternitz, G.H. Loh, B. Black, J. Rupley, P.G. Sassone, W. Attrot, Y. Wu International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Oct. 2008 |
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Static Strands: Safely Exposing Dependence Chains for Increasing Embedded Power Efficiency (updated reprint) P.G. Sassone, D.S. Wills, G.H. Loh ACM Transactions on Embedded Computing Systems (TECS), Vol. 6, No. 4, Sep. 2007 |
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Matrix Scheduler Reloaded P.G. Sassone, J.P. Rupley, N. Brekelbaum, G.H. Loh, B. Black Proceedings of International Symposium on Computer Architecture (ISCA), June 2007 |
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Static Strands: Safely Exposing Dependence Chains for Increasing Embedded Power Efficiency P.G. Sassone, D.S. Wills, G.H. Loh Proceedings of the Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), June 2005 |
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Scaling Up the Atlas Chip-Multiprocessor P.G. Sassone, D.S. Wills IEEE Transactions on Computers (ToC), Vol. 54, No. 1, Jan. 2005 |
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Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication P.G. Sassone, D.S. Wills Proceedings of the Symposium on Microarchitecture (MICRO-37), Dec. 2004 (Award for Best Student Presentation) |
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On the Extraction and Analysis of Prevalent Dataflow Patterns P.G. Sassone, D.S. Wills Proceedings of the Workshop on Workload Characterization (WWC-7), Oct. 2004 |
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Multicycle Broadcast Bypass: Too Readily Overlooked P.G. Sassone, D.S. Wills Proceedings of the Workshop on Complexity Effective Design (WCED), June 2004 |
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| Floorplanning |
Traffic: A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning P.G. Sassone, S.K. Lim IEEE Transactions on Computer-Aided Design (TCAD), Vol. 25, No. 6, June 2006 |
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A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning P.G. Sassone, S.K. Lim Proceedings of the International Conference on Computer Aided Design (ICCAD), Nov. 2003 |
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Distributed Systems
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A Browser-Based Framework for Rapid Federation Development C.V. Lenfest, P.G. Sassone, T.A. McLean Proceedings of the Spring 2004 Simulation Interoperability Workshop (SIW), Apr. 2004 |
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Efficient Bloom Filter M. Breternitz, Y. Wu, P.G. Sassone, J.P. Rupley, W. Attrot, B. Black Patent #7,620,781 |
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Scheduling a Direct Dependent Instruction P.G. Sassone, J.P. Rupley, B. Black Application Filed Oct. 2008 |
| Doctorate | Georgia Inst of Technology, Atlanta GA |
Aug. 2005 |
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Doctorate in Electrical and
Computer Engineering Thesis Title: Characterization and Avoidance of Critical Pipeline Resources in Aggressive Superscalar Processors Advisor: Prof. D. Scott Wills |
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| Masters | Georgia Inst of Technology, Atlanta GA |
May 2002 |
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Master of
Electrical and Computer Engineering Minor in Computer Science |
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| Bachelors | Georgia Inst of Technology, Atlanta GA |
Dec. 2000 |
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Bachelor of Computer Engineering Graduation with Honors Certificate of Economics One semester abroad studying at Oxford, UK |
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